We are about to come to the end of an era. Moore's law is coming up against fundamental limits. Right now the smallest transistors require hundreds to thousands of atoms. It will be hard to get transistors much smaller than that. In addition as transistors get smaller than that, overall circuits actually get slower and require more power.
Chip and IC equipment makers are at a crossroads as they enter an era that might be called "More than Moore."Currently chips are being made with photo lithography using ultraviolet light that has a wave length of 193 nm. So how do you make transistors with feature sizes of 22 nm using 193 nm light? With great difficulty.
The relentless pursuit of scaling over the last 40 years, in accordance with the famed postulate known as Moore's Law, continues to be an aggressive goal.
However, the buzz at the Semicon West equipment show last week suggests the time has come to rethink what is scalable and examine other ways of adding value to semiconductor devices.
Although leading IC makers Intel and IBM remain committed to Moore's Law (Intel in part out of respect for founder Gordon Moore's scaling formula), both are starting to address its limits. In addition, those limits are not just technical; they are economic as well.
Is it still practical?
At Semicon West, where the relentless market pressures facing chipmakers are measured in the progress of tools able to refine physical transistor gate lengths down to 22nm, the Greek chorus of industry gurus sounded a warning: In chasing after ever smaller and denser devices, it might just not be practical to go on scaling for the sake of scaling.
"It's been an economic issue all along," said keynoter Bernie Meyerson, an IBM fellow and CTO of the IBM Systems and Technology Group.
"Moore's Law stipulates that you need to double the density of chips every 12 to 18 months [for scaling purposes]; that's an economic, not a technical issue."
The recipe for scaling is expensive and geometries are approaching single atoms, which won't scale. Those facts are forcing the industry to look "beyond CMOS," simply because "the result of further scaling is more power consumption, more costly [devices] and slower operation," said Meyerson.
So what are some possible answers? Stacking chips is one answer. That assumes that you can get the power out of a 3D structure without raising temperatures excessively. Another possibility is more efficient computer languages that get more done with fewer instruction cycles. As many of you know I like FORTH for that purpose. It is a language that lends itself well to mechanization in silicon. Our premier language today, C and its variants - not so much. Another thing FORTH has going for it is that the number of transistors for a given processor (8 bit, 16 bit, 32 bit etc.) is much smaller than the number required for current designs. Fewer transistors means that the transistors will be closer together (that will speed things up because the speed of light is now a fundamental limitation) and fewer transistors also means less heat production. Heat slows down the kind of transistors used in computers (MOSFETs) and it also causes problems because that heat must be dissipated.
Quantum computing might also help. Except for a couple of things. The number of bits (Q bits) is currently small and quantum computing requires temperatures near absolute zero.
One thing to keep in mind is that we have at least another 10 years to go with what we currently know. We may find an answer in that time. Another thing that will help is that every 10 years we double the area that is produced per batch (wafer). That means that cost reductions will slow down if that is the best we can do. However, we still have a ways to go before cost reductions stop all together.
Cross Posted at Classical Values